This invention relates to the fabrication of microelectronic devices, and, more particularly, to the preparation of multilevel metallizations in such devices.
Thin-film microelectronic devices are typically prepared as a succession of overlying layers of metals, semiconductors, insulators, and possibly other materials. The various layers are deposited, patterned, and etched to form specific active or passive circuit elements, interconnections, insulations, etc. This technology has the important advantage that the microelectronic device may be made very small, and that thousands of circuit elements can be fabricated in a single integrated unit.
Individual layers and circuit elements often have dimensions in the range of a micrometer or less. With this fine scale and in view of the many layers and circuit elements that may be present, great care is required to avoid manufacturing defects. For example, the deposition of unwanted material, the removal of necessary material, or the introduction of contamination at a single location can lead to inoperability of the final product.
In one phase of thin-film microelectronic device fabrication, it is often necessary to deposit multiple patterned layers of electrically conductive metals overlying some active semiconductor circuit components. The metallization is usually provided to electrically interconnect different active elements as required by the overall device design. Because of the complexity of some of the circuit designs, a single level of metallization cannot satisfy the interconnection requirements. Multiple, three dimensionally interconnected metal layers are therefore sometimes required.
A layer of metal must be deposited onto a generally smooth, planar surface. Some degree of irregularity of the underlying surface is acceptable, but if the surface is too irregular the continuity of the metal may be lost or other defects may result. When a multilevel metallization is required, the first (bottom) layer is typically patterned into a series of planar leads, termed traces. These traces naturally constitute a surface irregularity for the deposition of succeeding layers. An insulator layer is usually applied over the first metal layer, but the insulator layer will have an irregular surface due to the underlying traces, unless care is taken to attain a planar surface.
Techniques are known for producing a more planar surface upon which the succeeding metallization may be deposited. One approach is a photoresist etchback procedure wherein a photoresist is deposited onto the surface, flowed, and etched back in a dry plasma etcher. Another approach is a spin-on technique in which a glassy insulator precursor is placed onto the irregular surface and spun while flowable to cause its upper surface to become more planar. The precursor is then heated to drive off solvent and form a glass insulator. Unfortunately, both of these approaches have drawbacks. Photoresist etchback depends upon the ability to co-etch different materials at the same rate, and that is difficult to achieve in practice. In practice, there is observed a high defect density in the final product. Both of these techniques are also relatively prone to introducing particulate and other contamination into the surface of the device. The contamination may be retained into the final device and adversely affect its electrical performance.
There is a need for an improved technique for fabricating multilevel metallizations in microelectronic devices. The present invention fulfills this need, and further provides related advantages.